This invention relates to a semiconductor device with a semiconductor substrate in which two insulated-gate field effect transistors and a thyristor element are formed. More particularly, this invention relates to a semiconductor device whose thyristor is capable of preventing the break-through, i.e., the error-trigger due to a transient surge voltage, and can be triggered at any time point in the voltage cycle appearing between the anode (A) and the cathode (K) of the thyristor.
Two prior art devices will be described by referring to the accompanying drawings. A first prior art device is a thyristor of the planar type, which is turned on by a small gate current. This thyristor will be referred to as a high by sensitive thyristor. A second prior art device is a high by sensitive semiconductor device of the planar type, which is free from break-through or spurious triggering caused by the transient voltage.
FIG. 1A shows, in cross sectional form, a prior art highly sensitive thyristor device, and FIG. 1B shows an equivalent circuit of the thyristor device. An example of the method of manufacturing the thyristor device will be described in brief. Separation region 1 for element separation is formed in N.sup.- semiconductor substrate 50 with resistivity of 40 to 50 .OMEGA.cm. Region 1 separates the thyristor under discussion from other elements (not shown). Base layer 2 of the P conductivity type is formed in a first major surface layer (the upper surface region as viewed in the drawing) of substrate 50. At the same time, emitter layer 3 of the P conductivity type is formed in a second major surface layer (the lower surface region in the drawing) of substrate 50. P emitter region 3 also serves as an anode region of the thyristor element. Emitter layer 4 of the N conductivity type, which also serves as a cathode region of the thyristor element, is formed in the surface region of P base layer 2. Reference characters A, K and G, respectively, designate an anode terminal, a cathode terminal and a gate terminal, which are connected, via electrode wiring, to the P emitter layer (anode region), the N emitter layer (cathode region), and the base layer, respectively.
This thyristor device is used as a thyristor handling a relatively small current, e.g., 3A, and has the characteristic that the gate trigger current is very small, approximately several tens .mu.A. When this thyristor is soley used, it is readily triggered by the leakage current due to high temperature and transient current induced by external surge voltages. In practical use, a resistor is externally connected between the gate (G) and the cathode (K), to reduce the gate trigger current to about 1 mA.
Turning now to FIGS. 2A and 2B, there are shown a cross sectional view of a high sensitivity thyristor device which is capable of preventing spurious triggering due to transient voltages. FIG. 2B is an equivalent circuit of that thyristor. Throughout the drawings, like symbols are used to designate like or equivalent elements. As seen from the drawing, this thyristor device is additionally provided with P well region 5 and P layer 34. Formed in P well region 5 are N drain layer 7, N source layer 8, gate oxide film 9 and gate electrode 10, which form a MOS FET functioning to prevent breakthrough. N layer 11 is also provided in P well region 5, in order to protect the gate oxide film of the FET. This N layer cooperates with P well region 5 to form a Zener diode.
The thyristor device thus structured is capable of turning on the thyristor by a minute gate trigger current, e.g., about 30 .mu.A to 5 .mu.A, and further is free from break-through due to transient and leakage currents. The electrodes (G and K) are almost short-circuited by the MOS FET element at all times, which is formed between these electrodes. Therefore, leakage transient currents are by-passed through the MOS FET. The voltage across electrodes G and K is kept below the forward voltage (0.5 to 0.6 V) at the PN junction between the cathode region 4 (N emitter layer 4) and the P base layer 2. The prior thyristor device has the advantages as mentioned above; however, it is disadvantageous in that it cannot be triggered at any phase of the A-K voltage (V.sub.AK). Since the MOS FET is driven through P layer 34 by voltage V.sub.AK, the voltage able to trigger the thyristor is below the gate threshold voltage of the MOS FET, and ranges approximately from 0 to 5 V. For this reason, when voltage V.sub.AK is above 5 V, even if the gate input signal is applied to the thyristor, the thyristor element is not triggered until the next cycle of voltage V.sub.AK. In other words, under this condition, the trigger of the thyristor is delayed a maximum of about 20 msec (when the frequency of the power source is 50 Hz).
Incidentally, resistor R.sub.GK inserted between electrodes G and K is provided for limiting the trigger current to a desired value, e.g., 5 .mu.A.
To reduce the size of the gate power source for the thyristor device, there is a strong demand to develop thyristor devices with a high gate sensitivity or triggerable by a small gate trigger current. The prior thyristor devices with high sensitivity shown in FIGS. 1A and 1B can be triggered by very small trigger current, 10 .mu.A. This fact, however, implies that it is very sensitive to external transient voltages or it is readily broken through by transient voltages. To avoid this, the by-pass resistor is externally connected between electrodes G and K. However, use of the by-pass resistor results in an increase of the gate trigger current to about 1 mA.
The thyristor device of FIGS. 2A and 2B has been developed as the thyristor element which is free from break-through due to transient surge voltages, however, it is triqgerable by a small gate trigger current, e.g., 5 to 30 .mu.A. Indeed, this thyristor device succeeded in solving sensitivity and breakthrough problems, but it suffers from another problem that the period allowing the thyristor to be triggered is very short. This new problem arises from the fact that the voltage between electrodes A and K is below the threshold voltage of the MOS FET.